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Preliminary
Product Description
Sirenza Microdevices' SXA-3318B amplifier is a high efficiency GaAs Heterojunction Bipolar Transistor (HBT) MMIC housed in a low-cost surface-mountable plastic package. These HBT MMICs are fabricated using molecular beam epitaxial growth technology which produces reliable and consistent performance from wafer to wafer and lot to lot. These amplifiers are specially designed for use as driver devices for infrastructure equipment in the 400-2500 MHz cellular, ISM, WLL, PCS, W-CDMA applications. Its high linearity makes it an ideal choice for multi-carrier as well as digital applications.
SXA-3318B
400-2500 MHz Balanced 1/2 W Medium Power GaAs HBT Amplifier with Active Bias
Product Features
* On-chip Active Bias Control * Balanced for excellent input/output VSWR and minimized reflections * High OIP3 : +47 dBm typ. * High P1dB : +28 dBm typ. * Patented High Reliability GaAs HBT Technology * Surface-Mountable Power Plastic Package
5V
SXA-3318B
RFin
1 2 3 4
8 7 6 5
RFout
Applications
* W-CDMA, PCS, Cellular Systems * High Linearity IF Amplifiers * Multi-Carrier Applications
Symbol Parameters: Test Conditions: Z0 = 50 Ohms, Ta = 25C Output Power at 1dB Compression f = 850 MHz f = 1960 MHz f = 2140 MHz f = 850 MHz f = 1960 MHz f = 2140 MHz f = 850 MHz f = 1960 MHz f = 2140 MHz f = 850 MHz f = 1960 MHz f = 2140 MHz f = 880 MHz f = 1960 MHz f = 2140 MHz f = 850 MHz f = 1960 MHz f = 2140 MHz V cc = 5 V Units Min. Typ. 27.5 28.0 28.0 17.5 12.8 12.0 1.3:1 1.2:1 1.2:1 47 47 48 -55 -55 -50 4.5 5.1 5.1 240 70* Max.
P 1dB
dB m 27.0 dB 10.5 -
S 21
Small signal gain
13.5
S11,S22
Input/Output VSWR
OIP3
Output Third Order Intercept Point (Pout/Tone = +11 dBm, Tone spacing = 1 MHz) Adjacent Channel Power: IS-95 at POUT = 19 dBm IS-95 at POUT = 19 dBm W-CDMA at POUT = 18 dBm Noise Figure Device Current (120 mA per amplifier) Thermal Resistance (junction - lead) per amplifier *Note: 2 amplifiers per packaged part
dB m 45 dB c
AC P
NF ID Rth, j-l
dB mA C/W
The information provided herein is believed to be reliable at press time. Sirenza Microdevices assumes no responsibility for inaccuracies or omissions. Sirenza Microdevices assumes no responsibility for the use of this information, and all such information shall be entirely at the user's own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. Sirenza Microdevices does not authorize or warrant any Sirenza Microdevices product for use in life-support devices and/or systems. Copyright 2003 Sirenza Microdevices, Inc. All worldwide rights reserved.
303 South Technology Ct., Broomfield, CO 80021
Phone: (800) SMI-MMIC
http://www.sirenza.com
EDS-103164 Rev A
1
Preliminary
Note: Tested in Balanced Configuration shown in Application Circuit, tuned for Output IP3 P1dB vs. Frequency
30 29 28 27 2 5C 26 25 0 .8 0 .8 5
GHz
dB
850 MHz Application Circuit Data, VCC= 5V, ID= 240mA
Gain vs. Frequency
25 22 19 16 -40 C 8 5C 10 13 2 5C -40 C 8 5C 0 .9 5 0 .8 0 .85
GHz
dBm
0 .9
0 .9
0 .95
Input/Output Return Loss, Isolation vs. Frequency, T=25C
0 -5 -1 0 -1 5
dB
55
S 11 S 22 S 12
dBm
Third Order Intercept vs. Frequency (POUT per tone = 11dBm)
50 45 40 35 30 25C -40C 85C
-2 0 -2 5 -3 0 -3 5 -4 0 0 .8 0 .8 5
GHz
0 .9
0 .9 5
0.8
0.85
GHz
0.9
0.95
55 50 45
Third Order Intercept vs. Tone Power Frequency = 880 MHz
25C -40C 85C
-40 -45 -50 -55
dBc
880 MHz Adjacent Channel Power vs. Channel Output Power
dBm
-60 -65 -70 -75 25C -40C 85C 15 16 17 18 19 20 21 22
40 35 30 5 10 15
POUT per tone (dBm)
-80
20 25
Channel Output Power (dBm) IS-95, 9 Channels Forward
303 South Technology Ct., Broomfield, CO 80021
Phone: (800) SMI-MMIC
http://www.sirenza.com
EDS-103164 Rev A
2
Preliminary
1960 MHz Application Circuit Data, VCC= 5V, ID= 240mA
P1dB vs. Frequency
30 29 28 27 25 C 26 25 1.9 3 -40C 85 C 1.9 4 1.9 5 1.9 6
GHz
dB
Note: Tested in Balanced Configuration shown in Application Circuit, tuned for Output IP3 Gain vs. Frequency
20 17 14 11 8 5 1.9 3 25 C -40C 85 C 1.9 9 1.9 4 1.9 5 1.9 6
GHz
dBm
1.9 7
1.9 8
1.9 7
1.9 8
1.9 9
Input/Output Return Loss, Isolation vs. Frequency, T=25C
0 -5 -1 0 -1 5 -2 0 -2 5 -3 0 -3 5 -4 0 1 .9 3 1 .9 4 1 .9 5 1 .9 6
GHz
dBm dB
Third Order Intercept vs. Frequency (POUT per tone = 11dBm)
55 50 45 40 35 30 1.93 25C -40C 85C
S11 S22 S12
1 .9 7
1 .9 8
1 .9 9
1.94
1.95
1.96
GHz
1.97
1.98
1.99
Third Order Intercept vs. Tone Power Frequency = 1.96 GHz
55 50 45
dBc
1960 MHz Adjacent Channel Power vs. Channel Output Power
-4 0 -4 5 -5 0 -5 5 -6 0 -6 5 25C -4 0C 85C 15 16 17 18 19 20 21 22
dBm
40 25C 35 30 5 10 15
POUT per tone (dBm)
-40C 85C 20 25
-7 0 -7 5 -8 0
Channel Output Power (dBm) IS-95, 9 Channels Forward
303 South Technology Ct., Broomfield, CO 80021
Phone: (800) SMI-MMIC
http://www.sirenza.com
EDS-103164 Rev A
3
Preliminary
2140 MHz Application Circuit Data, VCC= 5V, ID= 240mA
Note: Tested in Balanced Configuration shown in Application Circuit, tuned for Output IP3
P1dB vs. Frequency
30 29 28
dB
Gain vs. Frequency
20 17 14 11 25 C -40C 85 C 8 5 2.11 25C -40C 85C 2.1 7 2.12 2.13 2.14
GHz
dBm
27 26 25 2.1 1
2.1 2
2.1 3
2.1 4
GHz
2.1 5
2.1 6
2.15
2.16
2.17
Input/Output Return Loss, Isolation vs. Frequency, T=25C
0 -5 -10 -15 -20 -25 -30 -35 -40 2.11 2.12 2.13 2.14
GHz
dBm dB
Third Order Intercept vs. Frequency (POUT per tone = 11dBm)
55
S 11 S 22 S 12
50 45 40 35 30 2.11 25C -40C 85C 2.12 2.13 2.14
GHz
2.15
2.16
2.17
2.15
2.16
2.17
Third Order Intercept vs. Tone Power Frequency = 2.14 GHz
55 50 45
dBc
2140 MHz Adjacent Channel Power vs. Channel Output Power
-40
25C -40C 85C
-45 -50 -55 -60 -65 25C -40C 85C 15 16 17 18 19 20 21 22
dBm
40 35 30 5 10 15
POUT per tone (dBm)
20
25
Channel Output Power (dBm) W-CDMA, 64 DPCH + Overhead
303 South Technology Ct., Broomfield, CO 80021
Phone: (800) SMI-MMIC
http://www.sirenza.com
EDS-103164 Rev A
4
Preliminary Application Schematic (850 MHz)
C6 C5 C4 C3
VCC
RF IN
X1
C1 C2 C1 C2
Z=50, EL1 Z=50, EL1
L1
Z=50, EL2
SXA-3318B
1 2,3 4 8 6,7 5
L2
Z=50, EL3
C3 C7
R1 x2
R1 x2
L1
Z=50, EL2
Z=50, EL3
L2
C7 C3
X1
RF OUT
C6
C5
C4
C3
VCC
Ref. Des. C 1, C 3 C2 C4 C5 C6 C7 L1 Vendor Series Rohm MCH18 Rohm MCH18 Rohm MCH18 Rohm TAJB104KLRH Rohm TAJB106K020R Rohm MCH18 Toko LL1608-FS 850 MHz 47pF, 5% 3.9pF, 0.25pF 1000pF, 5% 0.1uF, 10% 10uF, 10% 3.3pF, 0.25pF 1.2nH, 0.3nH Ref. Des. L2 E L1 E L2 E L3 X1 R1 Vendor Series Toko LL1608-FS 50 Ohms 50 Ohms 50 Ohms Sirenza Coupler Rohm MCR100J 850 MHz 33nH, 5% 9.9 4.4 11 AH03L 100 Ohm, 5%
Evaluation Board Layout (850 MHz)
SIRENZA
MICRODEVICES
X1
Vcc C6
+
R1 x2 X1
L2 C1 C2 L1
C5 C4 C3 C7
C3 C4 C5 R1 x2 Balanced SOIC-8 Eval Board ECB-103109-A Vcc
+
C6
303 South Technology Ct., Broomfield, CO 80021
Phone: (800) SMI-MMIC
http://www.sirenza.com
EDS-103164 Rev A
5
Preliminary Application Schematic (1960 MHz, 2140 MHz)
VCC
C5 C4 C3
RF IN
X1
C1 C2 C1 C2
Z=50, EL1 Z=50, EL1
SXA-3318B
1 2,3 4 8 6,7 5
L1
Z=50, EL2
C3 C7
R1 x2
R1 x2
Z=50, EL2
L1
C7 C3
X1
RF OUT
C5
C4
C3
VCC
Ref. Des. C 1, C 3 C2 C4 C5 C7
Vendor Series Rohm MCH18 Rohm MCH18 Rohm MCH18 Rohm TAJB104KLRH Rohm MCH18
1960 MHz 22pF, 5% 1.2pF, 0.25pF 1000pF, 5% 0.1uF, 10% 1.0pF, 0.25pF
2140 MHz 22pF, 5% 1.2pF, 0.25pF 1000pF, 5% 0.1uF, 10% 1.0pF, 0.25pF
Ref. Des. L1 E L1 E L2 X1 R1
Vendor Series Toko LL1608-FS 50 Ohms 50 Ohms Sirenza Coupler Rohm MCR100J
1960 MHz 18nH, 5% 10.1 20.9 AM03M 100 Ohm, 5%
2140 MHz 18nH, 5% 11 22.8 AM03M 100 Ohm, 5%
Evaluation Board Layout (1960 MHz, 2140 MHz)
Vcc
X1
X1 L1 C1 C2 C7 C5 C4 C3
R1 x2
C3 C4 C5 R1 x2 ECB-102363 Rev. A Balanced SOIC-8 Eval Board Vcc Sirenza Microdevices
303 South Technology Ct., Broomfield, CO 80021
Phone: (800) SMI-MMIC
http://www.sirenza.com
EDS-103164 Rev A
6
Preliminary
Pin # 1, 4 2, 3, 6, 7
Function RF In GND
Description RF input pin. This pin requires the use of an external DC blocking capacitor. Connection to ground. Use via holes to reduce lead inductance. Place vias as close to ground leads as possible.
Device Schematic
1 2 3 4
5, 8
RF Out/Vcc RF output and bias pin. Bias should be supplied to this pin through an external RF choke. Because DC biasing is present on this pin, a DC blocking capacitor should be used in most applications (see application schematic). The supply side of the bias network should be well bypassed. An output matching network is necessary for optimum performance. GND Exposed area on the bottom side of the package needs to be soldered to the ground plane of the board for thermal and RF performance. Several vias should be located under the EPAD as shown in the recommended land pattern (page 8).
Input Match
Active Bias
8 7 6
Active Bias Input Match
5
EPAD
Device Current vs. Source Voltage
350
Absolute Maximum Ratings
Parameter Max. Supply Current (ID) per amplifier (2 amplifiers per packaged part) Max. Device Voltage (VCC) Max. Power Dissipation per amplifier (2 amplifiers per packaged part) Max. RF Input Power per amplifier (2 amplifiers per packaged part) Max. Junction Temp. (TJ) Absolute Limit 240 mA 6.0 V 1500 mW 100 mW +160 C -40 to +85 C +150 C
Device Current (mA)
300 250 200 150 100 50 0 0 1
-40 C 25 C 85 C
2
3
4
5
6
Operating Lead Temp. (TL) Max. Storage Temp.
VS (V)
Operation of this device beyond any one of these limits may cause permanent damage. For reliable continuous operation, the device voltage and current must not exceed the maximum operating values specified in the table on page one. Bias Conditions should also satisfy the following expression: IDVCC (max) < (TJ - TL)/Rth,j-l
ESD: Class 1B (Passes 500V ESD pulse) Appropriate precautions in handling, packaging and testing devices must be observed. Moisture Sensitivity Level: Level 1 (MSL-1) No special moisture packaging/handling is required during storage, shipment, or installation of the devices.
303 South Technology Ct., Broomfield, CO 80021
Phone: (800) SMI-MMIC
http://www.sirenza.com
EDS-103164 Rev A
7
Preliminary
Recommended Land Pattern
0.150 [3.81] Plated-Thru Holes (0.015" Dia, 0.030" Pitch) Machine Screws 0.080 [2.03] 0.050 [1.27] 0.020 [0.51] 0.140 [3.56]
Part Number Ordering Information
Part Number Devices Per Reel Reel Siz e
SXA-3318B 500 7"
Part Symbolization
0.300 [7.62]
The part will be symbolized with a "SXA3318B" designator on the top surface of the package.
Package Outline Drawing (See SMDI MPO-101644 for tolerances)
8 7 6 5 .194 [4.93] EXPOSED PAD
.236 [5.994] .155 [3.937]
XXXX SXA 3318B
1 2 3 .045 [1.143] .035 [.889] 4 Beveled Edge
.09 [2.286]
.130 [3.302] BOTTOM VIEW
TOP VIEW .050 [1.27] .016 [.406] .061 [1.549] .008 [.203] .058 [1.473]
.013 [.33] x 45
.008
.194 [4.928] .003 [.076] SIDE VIEW SEATING PLANE SEE DETAIL A
.155 [3.937]
END VIEW
PARTING LINE
.025 5 DETAIL A
Note: XXXX represents the lot code DIMENSIONS ARE IN INCHES [MM]
303 South Technology Ct., Broomfield, CO 80021
Phone: (800) SMI-MMIC
http://www.sirenza.com
EDS-103164 Rev A
8

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